Advances in MOS Memory Technology

Résumé du livre

In this thesis, several important semiconductor memory design issues related to de-posited dielectric and polysilicon layers have been investigated. This study enabled the development of a novel negative resistance MOS device which has the potential to be used in a low-area, low power static memory. In all Non-Volatile Memory (NVM) cells, capacitive coupling between deposited layers determines the operation of the memory. A combination of numerical simulation and characterization techniques was used to evaluate and improve existing characterization methods for extracting capacitive coupling coefficients. In addition, the effect of polysilicon depletion on NVM performance was evaluated using numerical simulation techniques. Reliability of insulating layers, primarily oxides, is a primary-concern for all MOS based memories. In the case of NVM cells, the oxide reliability limits the programming speed of the device. A common characterization method for extracting trapped charge in oxides after Fowler-Nordheim stress is investigated and guidelines to improve the accuracy of the technique are proposed and verified using measurements. A novel modeling method for extracting interface states after hot-carrier stress is proposed and excellent agreement with measurements is obtained. As CMOS scaling approaches reach fundamental physical limits, novel device technologies are being researched to increase performance without scaling. A novel CMOS negative resistance device is proposed and verified using numerical simulation techniques. This device, used in a latch configuration, has the potential to replace existing RAM for low power embedded memory applications.