A Discrete Systematic Model for Racing in an SR Latch

Résumé du livre

Abstract: "This paper develops a model of propagational delay for digital logic which assumes all voltages to be boolean valued. This allows for calculations on racing which can not normally be done with only boolean valued models. To illustrate this point the paper goes through a particular instance of how a latch performs meta-stably when its set and reset inputs are made 1 simultaneously, and then simultaneously made 0. The extra ingredient which generates the propagational delay is the incorporation of a value for the MOSFET SiO2/Si interface charge. That charge is then modeled as varying in a linear way over time with changes in the gate value."