Sidewall Defects in Selective Epitaxial Growth (SEG) of Silicon and a 3-dimensional BiCMOS Bipolar Transistor

Résumé du livre

Abstract: "The objective of this work is to study the defects of the SEG/insulator sidewall interface as applied to the novel 3-dimensional structures. The defects were characterized through electrical measurements of a p+/n diode and transmission electron microscopy. Different mechanisms have been postulated to be responsible for these defects. These include thermal stress induced defects, defect nucleation close to the sidewall, and defects at the interface due to weak bonding. The simple structure of the diode allowed the design of many experiments in order to study the dependence of the sidewall defects on process conditions and other parameters and to identify the mechanisms controlling these defects