FPGA Implementation of a Contrast Enhancement Algorithm with Discriminative Filtering

Résumé du livre

[ANGLÈS] This project is the continuation of a research work focused on improving the current popular techniques for contrast enhancement in images. There are stills produced under very poor acquisition conditions, such as high dynamic range images or medical images that require those techniques in order to reveal details that otherwise remain hidden to the human eye. The problem is, those contrast enhancement algorithms (like Contrast Limited Adaptive Histogram Equalization - CLAHE) can reveal not just the detail of the image but also the noise hidden in it, making it hard to distinguish between the relevant information and the invented detail. As part of the research activity in image processing of Concordia University, an algorithm able to improve those results under certain conditions was developed by a student as her master thesis. This algorithm generates binary masks that attempt to detect the image noise using the source image. Then, a version of the image with CLAHE applied is low-pass filtered only where the pixels are detected as noise by those masks. The work in this project is based in that thesis, and it studies the behavior, performance and possibilities of the algorithm as a hardware (FPGA) implementation. The chosen description language was VHDL. To do so, a top-down bottom-up design approach has been employed.